| 431 | } |
| 432 | |
| 433 | void DataTransfer::Init() noexcept |
| 434 | { |
| 435 | // Initialise transfer ready pin |
| 436 | SetPinMode(SbcTfrReadyPin, OUTPUT_LOW); |
| 437 | |
| 438 | // Allocate buffers in SBC mode |
| 439 | #if HAS_LWIP_NETWORKING |
| 440 | // We are going try allocating the transfer buffer memory from the PBUF pool. |
| 441 | // In SAME70 builds we are relying on the PBUF pool size being large enough to accommodate both transfer buffers, because they must be in non-cached RAM. |
| 442 | InitAllocationFromPbufPool(); // we are not using a wired Ethernet interface on the Duet so we can use the PBUF pool memory |
| 443 | { |
| 444 | void *const mem = AllocateFromPbufPool(SbcTransferBufferSize); |
| 445 | # if SAME70 |
| 446 | rxBuffer = (char *)mem; // we MUST allocate from the PBUF pool because we need the memory to be non-cached |
| 447 | # else |
| 448 | rxBuffer = (mem != nullptr) ? (char *)mem : (char *)new uint32_t[(SbcTransferBufferSize + 3)/4]; |
| 449 | # endif |
| 450 | } |
| 451 | { |
| 452 | void *const mem = AllocateFromPbufPool(SbcTransferBufferSize); |
| 453 | # if SAME70 |
| 454 | txBuffer = (char *)mem; |
| 455 | # else |
| 456 | txBuffer = (mem != nullptr) ? (char *)mem : (char *)new uint32_t[(SbcTransferBufferSize + 3)/4]; |
| 457 | # endif |
| 458 | } |
| 459 | #elif SAME70 |
| 460 | # error Must allocate buffers from non-cached RAM |
| 461 | #else |
| 462 | rxBuffer = (char *)new uint32_t[(SbcTransferBufferSize + 3)/4]; |
| 463 | txBuffer = (char *)new uint32_t[(SbcTransferBufferSize + 3)/4]; |
| 464 | #endif |
| 465 | |
| 466 | #if SAME5x |
| 467 | // Initialize SPI |
| 468 | for (Pin p : SbcSpiSercomPins) |
| 469 | { |
| 470 | SetPinFunction(p, SbcSpiSercomPinsMode); |
| 471 | } |
| 472 | |
| 473 | Serial::EnableSercomClock(SbcSpiSercomNumber); |
| 474 | spi_dma_disable(); |
| 475 | |
| 476 | SbcSpiSercom->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; |
| 477 | while (SbcSpiSercom->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) { }; |
| 478 | SbcSpiSercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_DIPO(3) | SERCOM_SPI_CTRLA_DOPO(0) | SERCOM_SPI_CTRLA_MODE(2); |
| 479 | SbcSpiSercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN; |
| 480 | while (SbcSpiSercom->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_MASK) { }; |
| 481 | SbcSpiSercom->SPI.CTRLC.reg = SERCOM_SPI_CTRLC_DATA32B; |
| 482 | #else |
| 483 | // Initialize SPI |
| 484 | SetPinFunction(APIN_SBC_SPI_MOSI, SBCPinPeriphMode); |
| 485 | SetPinFunction(APIN_SBC_SPI_MISO, SBCPinPeriphMode); |
| 486 | SetPinFunction(APIN_SBC_SPI_SCK, SBCPinPeriphMode); |
| 487 | SetPinFunction(APIN_SBC_SPI_SS0, SBCPinPeriphMode); |
| 488 | |
| 489 | spi_enable_clock(SBC_SPI); |
| 490 | spi_disable(SBC_SPI); |
no test coverage detected