(self, data)
| 280 | self.cur_highmem_page = data[0] |
| 281 | |
| 282 | def ext_module_id(self, data): |
| 283 | out = ["Power level %d module" % ((data[0] >> 6) + 1)] |
| 284 | if data[0] & 0x20 == 0: |
| 285 | out.append("CDR") |
| 286 | if data[0] & 0x10 == 0: |
| 287 | out.append("TX ref clock input required") |
| 288 | if data[0] & 0x08 == 0: |
| 289 | self.have_clei = True |
| 290 | self.annotate("Extended id", ', '.join(out)) |
| 291 | |
| 292 | def connector(self, data): |
| 293 | if data[0] in CONNECTOR: |