Decoder's main data interpretation loop.
(self)
| 448 | return (v >> d) == 1 |
| 449 | |
| 450 | def decode(self): |
| 451 | '''Decoder's main data interpretation loop.''' |
| 452 | |
| 453 | # Signal conditions tracked by the protocol decoder: |
| 454 | # - Rising and falling RST edges, which span the width of a |
| 455 | # high-active RESET pulse. RST has highest priority, no |
| 456 | # other activity can take place in this period. |
| 457 | # - Rising and falling CLK edges when RST is active. The |
| 458 | # CLK pulse when RST is asserted will reset the card's |
| 459 | # address counter. RST alone can terminate memory reads. |
| 460 | # - Rising and falling CLK edges when RST is inactive. This |
| 461 | # determines the period where BIT values are valid. |
| 462 | # - I/O edges during high CLK. These are START and STOP |
| 463 | # conditions that tell COMMAND and DATA phases apart. |
| 464 | # - Rise of I/O during internal processing. This expression |
| 465 | # is an unconditional part of the .wait() condition set. It |
| 466 | # is assumed that skipping this match in many cases is more |
| 467 | # efficient than the permanent re-construction of the .wait() |
| 468 | # condition list in every loop iteration, and preferrable to |
| 469 | # the maintainance cost of duplicating RST and CLK handling |
| 470 | # when checking I/O during internal processing. |
| 471 | ( |
| 472 | COND_RESET_START, COND_RESET_STOP, |
| 473 | COND_RSTCLK_START, COND_RSTCLK_STOP, |
| 474 | COND_DATA_START, COND_DATA_STOP, |
| 475 | COND_CMD_START, COND_CMD_STOP, |
| 476 | COND_PROC_IOH, |
| 477 | ) = range(9) |
| 478 | conditions = [ |
| 479 | {Pin.RST: 'r'}, |
| 480 | {Pin.RST: 'f'}, |
| 481 | {Pin.RST: 'h', Pin.CLK: 'r'}, |
| 482 | {Pin.RST: 'h', Pin.CLK: 'f'}, |
| 483 | {Pin.RST: 'l', Pin.CLK: 'r'}, |
| 484 | {Pin.RST: 'l', Pin.CLK: 'f'}, |
| 485 | {Pin.CLK: 'h', Pin.IO: 'f'}, |
| 486 | {Pin.CLK: 'h', Pin.IO: 'r'}, |
| 487 | {Pin.RST: 'l', Pin.IO: 'r'}, |
| 488 | ] |
| 489 | |
| 490 | ss_reset = es_reset = ss_clk = es_clk = None |
| 491 | while True: |
| 492 | |
| 493 | is_outgoing = self.state == 'OUT' |
| 494 | is_processing = self.state == 'PROC' |
| 495 | (rst,clk,io) = self.wait(conditions) |
| 496 | |
| 497 | # Handle RESET conditions, including an optional CLK pulse |
| 498 | # while RST is asserted. |
| 499 | if self.check_bit(COND_RESET_START): |
| 500 | self.flush_queued() |
| 501 | ss_reset = self.samplenum |
| 502 | es_reset = ss_clk = es_clk = None |
| 503 | continue |
| 504 | if self.check_bit(COND_RESET_STOP): |
| 505 | es_reset = self.samplenum |
| 506 | self.handle_reset(ss_reset or 0, es_reset, ss_clk and es_clk) |
| 507 | ss_reset = es_reset = ss_clk = es_clk = None |
nothing calls this directly
no test coverage detected