| 224 | self.putx([2, ['Unknown instruction: %s' % bits]]) |
| 225 | |
| 226 | def decode(self, ss, es, data): |
| 227 | cmd, val = data |
| 228 | |
| 229 | self.ss, self.es = ss, es |
| 230 | |
| 231 | if cmd != 'NEW STATE': |
| 232 | # The right-most char in the 'val' bitstring is the LSB. |
| 233 | val, self.samplenums = val |
| 234 | self.samplenums.reverse() |
| 235 | |
| 236 | if cmd == 'IR TDI': |
| 237 | # Switch to the state named after the instruction, or 'UNKNOWN'. |
| 238 | # The STM32F10xxx has two serially connected JTAG TAPs, the |
| 239 | # boundary scan tap (5 bits) and the Cortex-M3 TAP (4 bits). |
| 240 | # See UM 31.5 "STM32F10xxx JTAG TAP connection" for details. |
| 241 | self.state = ir.get(val[5:9], ['UNKNOWN', 0])[0] |
| 242 | bstap_ir = bs_ir.get(val[:5], ['UNKNOWN', 0])[0] |
| 243 | self.putf(4, 8, [1, ['IR (BS TAP): ' + bstap_ir]]) |
| 244 | self.putf(0, 3, [1, ['IR (M3 TAP): ' + self.state]]) |
| 245 | self.putx([2, ['IR: %s' % self.state]]) |
| 246 | |
| 247 | # State machine |
| 248 | if self.state == 'BYPASS': |
| 249 | # Here we're interested in incoming bits (TDI). |
| 250 | if cmd != 'DR TDI': |
| 251 | return |
| 252 | handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower()) |
| 253 | handle_reg(cmd, val) |
| 254 | self.state = 'IDLE' |
| 255 | elif self.state in ('IDCODE', 'ABORT', 'UNKNOWN'): |
| 256 | # Here we're interested in outgoing bits (TDO). |
| 257 | if cmd != 'DR TDO': |
| 258 | return |
| 259 | handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower()) |
| 260 | handle_reg(cmd, val) |
| 261 | self.state = 'IDLE' |
| 262 | elif self.state in ('DPACC', 'APACC'): |
| 263 | # Here we're interested in incoming and outgoing bits (TDI/TDO). |
| 264 | if cmd not in ('DR TDI', 'DR TDO'): |
| 265 | return |
| 266 | handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower()) |
| 267 | handle_reg(cmd, val) |
| 268 | if cmd == 'DR TDO': # Assumes 'DR TDI' comes before 'DR TDO'. |
| 269 | self.state = 'IDLE' |