(&self)
| 84 | /// stable since Skylake. |
| 85 | #[cfg(target_arch = "x86_64")] |
| 86 | fn raw_cache_config(&self) -> Option<u64> { |
| 87 | if !is_genuine_intel() { |
| 88 | // Not tested on AMD or other x86_64 vendors yet |
| 89 | return None; |
| 90 | } |
| 91 | // Retired load instructions, by the cache level that served them |
| 92 | // (demand loads only; stores and prefetches don't count). |
| 93 | match self { |
| 94 | // MEM_INST_RETIRED.ALL_LOADS: 0xD0 | 0x81 << 8 |
| 95 | PerfEvent::L1DCache => Some(0x81d0), |
| 96 | // MEM_LOAD_RETIRED.L1_MISS: 0xD1 | 0x08 << 8 |
| 97 | PerfEvent::L2DCache => Some(0x08d1), |
| 98 | // MEM_LOAD_RETIRED.L3_MISS: 0xD1 | 0x20 << 8 |
| 99 | PerfEvent::CacheMisses => Some(0x20d1), |
| 100 | _ => None, |
| 101 | } |
| 102 | } |
| 103 | |
| 104 | /// Raw PMU encoding of this cache slot on arm64: the architected PMU event |
| 105 | /// number, used directly as `perf_event_attr.config` for `PERF_TYPE_RAW`. |
no test coverage detected