Read from smbus the SPD content and interpret it for detecting memory attributes */
| 590 | |
| 591 | /** Read from smbus the SPD content and interpret it for detecting memory attributes */ |
| 592 | STATIC VOID read_smb(EFI_PCI_IO_PROTOCOL *PciIo, UINT16 vid, UINT16 did) |
| 593 | { |
| 594 | // EFI_STATUS Status; |
| 595 | UINT16 speed; |
| 596 | UINT8 i;// spd_size, spd_type; |
| 597 | UINT32 base, mmio, hostc; |
| 598 | UINT16 Command; |
| 599 | //RAM_SLOT_INFO* slot; |
| 600 | //BOOLEAN fullBanks; |
| 601 | UINT8* spdbuf; |
| 602 | // UINT16 vid, did; |
| 603 | |
| 604 | UINT8 TotalSlotsCount; |
| 605 | |
| 606 | smbPage = 0; // valid pages are 0 and 1; assume the first page (page 0) is already selected |
| 607 | // vid = gPci->Hdr.VendorId; |
| 608 | // did = gPci->Hdr.DeviceId; |
| 609 | |
| 610 | /*Status = */PciIo->Pci.Read ( |
| 611 | PciIo, |
| 612 | EfiPciIoWidthUint16, |
| 613 | PCI_COMMAND_OFFSET, |
| 614 | 1, |
| 615 | &Command |
| 616 | ); |
| 617 | |
| 618 | Command |= 1; |
| 619 | /*Status = */PciIo->Pci.Write ( |
| 620 | PciIo, |
| 621 | EfiPciIoWidthUint16, |
| 622 | PCI_COMMAND_OFFSET, |
| 623 | 1, |
| 624 | &Command |
| 625 | ); |
| 626 | |
| 627 | DBG("SMBus CmdReg: 0x%hX\n", Command); |
| 628 | |
| 629 | /*Status = */PciIo->Pci.Read ( |
| 630 | PciIo, |
| 631 | EfiPciIoWidthUint32, |
| 632 | 0x10, |
| 633 | 1, |
| 634 | &mmio |
| 635 | ); |
| 636 | if (vid == 0x8086) { |
| 637 | /*Status = */PciIo->Pci.Read ( |
| 638 | PciIo, |
| 639 | EfiPciIoWidthUint32, |
| 640 | 0x20, |
| 641 | 1, |
| 642 | &base |
| 643 | ); |
| 644 | |
| 645 | base &= 0xFFFE; |
| 646 | smbIntel = TRUE; |
| 647 | } |
| 648 | else { |
| 649 | /*Status = */PciIo->Pci.Read ( |
no test coverage detected