Function spi_read

core/spi.c:151–202

Read from the SPI range of ports */

/* Read from the SPI range of ports */
static uint8_t spi_read(uint16_t addr, bool peek) {
    static const uint16_t cr0_masks[16] = {
        0xF18C, 0xF8EF, 0xF0AC, 0xF3FC, 0xF18C, 0xF4C0, 0xF3AC, 0xF3AC,
        0xF18C, 0xFBEF, 0xF0AC, 0xF3FC, 0xF18C, 0xF4C0, 0xF3AC, 0xF3AC
    };

    uint32_t shift = (addr & 3) << 3, value = 0;
    switch (addr >> 2) {
        case 0x00 >> 2: // CR0
            value = spi.cr0;
            value &= cr0_masks[value >> 12 & 0xF];
            break;
        case 0x04 >> 2: // CR1
            value = spi.cr1;
            break;
        case 0x08 >> 2: // CR2
            value = spi.cr2;
            break;
        case 0x0C >> 2: // STATUS
            value = spi.tfve << 12 | spi.rfve << 4 |
                (spi.transferBits != 0) << 2 |
                (spi.tfve != SPI_TXFIFO_DEPTH) << 1 | (spi.rfve == SPI_RXFIFO_DEPTH) << 0;
            break;
        case 0x10 >> 2: // INTCTRL
            value = spi.intCtrl;
            break;
        case 0x14 >> 2: // INTSTATUS
            value = spi.intStatus;
            if (!peek) {
                spi.intStatus &= ~(1 << 1 | 1 << 0);
                intrpt_set(INT_SPI, spi.intCtrl & spi.intStatus);
            }
            break;
        case 0x18 >> 2: // DATA
            value = spi.rxFifo[spi.rfvi & (SPI_RXFIFO_DEPTH - 1)];
            if (!peek && !shift && spi.rfve) {
                spi.rfvi++;
                spi.rfve--;
                spi_update();
            }
            break;
        case 0x60 >> 2: // REVISION
            value = 0x01 << 16 | 0x21 << 8 | 0x00 << 0;
            break;
        case 0x1C >> 2:
        case 0x64 >> 2: // FEATURE
            value = SPI_FEATURES << 24 | (SPI_TXFIFO_DEPTH - 1) << 16 |
                (SPI_RXFIFO_DEPTH - 1) << 8 | (SPI_WIDTH - 1) << 0;
            break;
    }
    return value >> shift;
}

/* Write to the SPI range of ports */
static void spi_write(uint16_t addr, uint8_t byte, bool poke) {