| 628 | } |
| 629 | |
| 630 | uint8_t mem_read_cpu(uint32_t addr, bool fetch) { |
| 631 | uint8_t value = 0; |
| 632 | uint32_t ramAddr, select; |
| 633 | |
| 634 | addr &= 0xFFFFFF; |
| 635 | #ifdef DEBUG_SUPPORT |
| 636 | if (!fetch) { |
| 637 | debug_stack_entry_t *entry = &debug.stack[debug.stackIndex]; |
| 638 | if (entry->mode == cpu.L) { |
| 639 | if (entry->stack - addr <= 2 + (uint32_t)entry->mode) { |
| 640 | entry->popped = true; |
| 641 | } |
| 642 | if ((uint32_t)entry->retAddr + entry->range == addr) { |
| 643 | if (!++entry->range) { |
| 644 | --entry->range; |
| 645 | } |
| 646 | } |
| 647 | } |
| 648 | if (debug.addr[addr] & DBG_MASK_READ) { |
| 649 | debug_open(DBG_WATCHPOINT_READ, addr); |
| 650 | } |
| 651 | } |
| 652 | #endif |
| 653 | switch((addr >> 20) & 0xF) { |
| 654 | /* FLASH */ |
| 655 | case 0x0: case 0x1: case 0x2: case 0x3: |
| 656 | case 0x4: case 0x5: case 0x6: case 0x7: |
| 657 | case 0x8: case 0x9: case 0xA: case 0xB: |
| 658 | value = mem_read_flash(addr); |
| 659 | if (fetch && detect_flash_unlock_sequence(value)) { |
| 660 | control.flashUnlocked |= 1 << 3; |
| 661 | } |
| 662 | break; |
| 663 | |
| 664 | /* UNMAPPED */ |
| 665 | case 0xC: |
| 666 | value = mem_read_unmapped_other(true); |
| 667 | cpu.cycles += asic.serFlash ? 2 : 258; |
| 668 | break; |
| 669 | |
| 670 | /* RAM */ |
| 671 | case 0xD: |
| 672 | sched_process_pending_dma(4); |
| 673 | ramAddr = addr & 0x7FFFF; |
| 674 | if (ramAddr < 0x65800) { |
| 675 | value = mem.ram.block[ramAddr]; |
| 676 | } else { |
| 677 | value = mem_read_unmapped_ram(true); |
| 678 | } |
| 679 | break; |
| 680 | |
| 681 | /* MMIO <-> Advanced Perphrial Bus */ |
| 682 | case 0xE: case 0xF: |
| 683 | if (mmio_mapped(addr, select)) { |
| 684 | value = port_read_byte(mmio_port(addr, select)); |
| 685 | } else { |
| 686 | if (addr >= 0xFB0000 && addr < 0xFF0000) { |
| 687 | cpu.cycles += 3; |
no test coverage detected