| 77 | |
| 78 | /* eZ80 CPU State */ |
| 79 | typedef struct eZ80cpu { |
| 80 | eZ80registers_t registers; |
| 81 | eZ80context_t context; |
| 82 | uint32_t seconds, cycles, eiDelay, next; |
| 83 | uint64_t baseCycles, haltCycles, dmaCycles; |
| 84 | uint32_t flashTotalAccesses, flashCacheMisses; |
| 85 | int64_t flashDelayCycles; |
| 86 | uint8_t prefetch; |
| 87 | struct { |
| 88 | bool NMI : 1; /* Non-Maskable interrupt */ |
| 89 | bool IEF1 : 1; /* Interrupt enable flag 1 */ |
| 90 | bool IEF2 : 1; /* Interrupt enable flag 2 */ |
| 91 | bool ADL : 1; /* ADL bit */ |
| 92 | bool MADL : 1; /* Mixed-Memory modes */ |
| 93 | uint8_t IM : 2; /* Current interrupt mode */ |
| 94 | |
| 95 | /* Internal use: */ |
| 96 | uint8_t PREFIX : 2; /* Which index register is in use. 0: hl, 2: ix, 3: iy */ |
| 97 | bool SUFFIX : 1; /* There was an explicit suffix */ |
| 98 | /*bool S : 1;*//* The CPU data block operates in Z80 mode using 16-bit registers. All addresses use MBASE. */ |
| 99 | bool L : 1; /* The CPU data block operates in ADL mode using 24-bit registers. Addresses do not use MBASE. */ |
| 100 | /*bool IS : 1;*//* The CPU control block operates in Z80 mode. */ |
| 101 | bool IL : 1; /* The CPU control block operates in ADL mode. */ |
| 102 | bool IEF_wait : 1; /* Wait for interrupt enable */ |
| 103 | bool halted : 1; /* Have we halted the CPU? */ |
| 104 | bool inBlock : 1; /* Are we processing a block instruction? */ |
| 105 | }; |
| 106 | } eZ80cpu_t; |
| 107 | |
| 108 | extern eZ80cpu_t cpu; |
| 109 |
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