| 3158 | } |
| 3159 | |
| 3160 | static void Exception_normal (int nr) |
| 3161 | { |
| 3162 | uae_u32 newpc; |
| 3163 | uae_u32 currpc = m68k_getpc(); |
| 3164 | uae_u32 nextpc; |
| 3165 | int sv = regs.s; |
| 3166 | int interrupt; |
| 3167 | int vector_nr = nr; |
| 3168 | bool g1 = false; |
| 3169 | |
| 3170 | cache_default_data |= CACHE_DISABLE_ALLOCATE; |
| 3171 | |
| 3172 | interrupt = nr >= 24 && nr < 24 + 8; |
| 3173 | if (interrupt) |
| 3174 | vector_nr = iack_cycle(nr); |
| 3175 | |
| 3176 | if (currprefs.cpu_model <= 68010) { |
| 3177 | g1 = generates_group1_exception(regs.ir); |
| 3178 | } |
| 3179 | |
| 3180 | exception_debug (nr); |
| 3181 | MakeSR (); |
| 3182 | |
| 3183 | |
| 3184 | if (!regs.s) { |
| 3185 | regs.usp = m68k_areg (regs, 7); |
| 3186 | if (currprefs.cpu_model >= 68020 && currprefs.cpu_model < 68060) { |
| 3187 | m68k_areg (regs, 7) = regs.m ? regs.msp : regs.isp; |
| 3188 | } else { |
| 3189 | m68k_areg (regs, 7) = regs.isp; |
| 3190 | } |
| 3191 | regs.s = 1; |
| 3192 | if (currprefs.mmu_model) |
| 3193 | mmu_set_super (regs.s != 0); |
| 3194 | } |
| 3195 | |
| 3196 | |
| 3197 | if ((m68k_areg(regs, 7) & 1) && currprefs.cpu_model < 68020) { |
| 3198 | if (nr == 2 || nr == 3) |
| 3199 | cpu_halt (CPU_HALT_DOUBLE_FAULT); |
| 3200 | else |
| 3201 | exception3_notinstruction(regs.ir, m68k_areg(regs, 7)); |
| 3202 | return; |
| 3203 | } |
| 3204 | if ((nr == 2 || nr == 3) && exception_in_exception < 0) { |
| 3205 | cpu_halt (CPU_HALT_DOUBLE_FAULT); |
| 3206 | return; |
| 3207 | } |
| 3208 | |
| 3209 | if (!currprefs.cpu_compatible) { |
| 3210 | addrbank *ab = &get_mem_bank(m68k_areg(regs, 7) - 4); |
| 3211 | // Not plain RAM check because some CPU type tests that |
| 3212 | // don't need to return set stack to ROM.. |
| 3213 | if (!ab || ab == &dummy_bank || (ab->flags & ABFLAG_IO)) { |
| 3214 | cpu_halt(CPU_HALT_SSP_IN_NON_EXISTING_ADDRESS); |
| 3215 | return; |
| 3216 | } |
| 3217 | } |
no test coverage detected