| 764 | } |
| 765 | |
| 766 | uae_u32 returnregx(int regid) |
| 767 | { |
| 768 | if (regid < BREAKPOINT_REG_PC) |
| 769 | return regs.regs[regid]; |
| 770 | switch(regid) |
| 771 | { |
| 772 | case BREAKPOINT_REG_PC: |
| 773 | return M68K_GETPC; |
| 774 | case BREAKPOINT_REG_USP: |
| 775 | return regs.usp; |
| 776 | case BREAKPOINT_REG_MSP: |
| 777 | return regs.msp; |
| 778 | case BREAKPOINT_REG_ISP: |
| 779 | return regs.isp; |
| 780 | case BREAKPOINT_REG_VBR: |
| 781 | return regs.vbr; |
| 782 | case BREAKPOINT_REG_SR: |
| 783 | MakeSR(); |
| 784 | return regs.sr; |
| 785 | case BREAKPOINT_REG_CCR: |
| 786 | MakeSR(); |
| 787 | return regs.sr & 31; |
| 788 | case BREAKPOINT_REG_CACR: |
| 789 | return regs.cacr; |
| 790 | case BREAKPOINT_REG_CAAR: |
| 791 | return regs.caar; |
| 792 | case BREAKPOINT_REG_SFC: |
| 793 | return regs.sfc; |
| 794 | case BREAKPOINT_REG_DFC: |
| 795 | return regs.dfc; |
| 796 | case BREAKPOINT_REG_TC: |
| 797 | if (currprefs.cpu_model == 68030) |
| 798 | return tc_030; |
| 799 | return regs.tcr; |
| 800 | case BREAKPOINT_REG_ITT0: |
| 801 | if (currprefs.cpu_model == 68030) |
| 802 | return tt0_030; |
| 803 | return regs.itt0; |
| 804 | case BREAKPOINT_REG_ITT1: |
| 805 | if (currprefs.cpu_model == 68030) |
| 806 | return tt1_030; |
| 807 | return regs.itt1; |
| 808 | case BREAKPOINT_REG_DTT0: |
| 809 | return regs.dtt0; |
| 810 | case BREAKPOINT_REG_DTT1: |
| 811 | return regs.dtt1; |
| 812 | case BREAKPOINT_REG_BUSC: |
| 813 | return regs.buscr; |
| 814 | case BREAKPOINT_REG_PCR: |
| 815 | return regs.pcr; |
| 816 | case BREAKPOINT_REG_FPIAR: |
| 817 | return regs.fpiar; |
| 818 | case BREAKPOINT_REG_FPCR: |
| 819 | return regs.fpcr; |
| 820 | case BREAKPOINT_REG_FPSR: |
| 821 | return regs.fpsr; |
| 822 | } |
| 823 | return 0; |
no test coverage detected