| 2571 | } |
| 2572 | |
| 2573 | void record_rom_access(uaecptr ptr, uae_u32 v, int size, bool rw) |
| 2574 | { |
| 2575 | dma_record_init(); |
| 2576 | if (!dma_record_data) |
| 2577 | return; |
| 2578 | struct dma_rec *dr = &dma_record_data[dma_record_cycle]; |
| 2579 | dr->miscaddr = ptr; |
| 2580 | dr->miscval = v; |
| 2581 | dr->ciarw = rw; |
| 2582 | dr->miscsize = size; |
| 2583 | } |
| 2584 | |
| 2585 | void record_cia_access(int r, int mask, uae_u16 value, bool rw, int phase) |
| 2586 | { |
no test coverage detected