| 2583 | } |
| 2584 | |
| 2585 | void record_cia_access(int r, int mask, uae_u16 value, bool rw, int phase) |
| 2586 | { |
| 2587 | dma_record_init(); |
| 2588 | if (!dma_record_data) |
| 2589 | return; |
| 2590 | |
| 2591 | struct dma_rec *dr = &dma_record_data[dma_record_cycle]; |
| 2592 | if (dr->ciaphase < 0) { |
| 2593 | return; |
| 2594 | } |
| 2595 | |
| 2596 | dr->ciamask = mask; |
| 2597 | dr->ciareg = r; |
| 2598 | dr->ciavalue = value; |
| 2599 | dr->ciarw = rw; |
| 2600 | dr->ciaphase = phase; |
| 2601 | } |
| 2602 | |
| 2603 | void record_dma_read(uae_u16 reg, uae_u32 addr, int type, int extra) |
| 2604 | { |
no test coverage detected