| 4369 | } |
| 4370 | |
| 4371 | static void memwatch_hit_msg(int mw) |
| 4372 | { |
| 4373 | console_out_f(_T("Memwatch %d: break at %08X.%c %c%c%c %08X PC=%08X "), mw, mwhit.addr, |
| 4374 | mwhit.size == 1 ? 'B' : (mwhit.size == 2 ? 'W' : 'L'), |
| 4375 | (mwhit.rwi & 1) ? 'R' : ' ', (mwhit.rwi & 2) ? 'W' : ' ', (mwhit.rwi & 4) ? 'I' : ' ', |
| 4376 | mwhit.val, mwhit.pc); |
| 4377 | for (int i = 0; memwatch_access_masks[i].mask; i++) { |
| 4378 | if (mwhit.access_mask == memwatch_access_masks[i].mask) |
| 4379 | console_out_f(_T("%s (%03x)\n"), memwatch_access_masks[i].name, mwhit.reg); |
| 4380 | } |
| 4381 | if (mwhit.access_mask & (MW_MASK_BLITTER_A | MW_MASK_BLITTER_B | MW_MASK_BLITTER_C | MW_MASK_BLITTER_D_N | MW_MASK_BLITTER_D_L | MW_MASK_BLITTER_D_F)) { |
| 4382 | blitter_debugdump(); |
| 4383 | } |
| 4384 | } |
| 4385 | |
| 4386 | static int memwatch_func (uaecptr addr, int rwi, int size, uae_u32 *valp, uae_u32 accessmask, uae_u32 reg) |
| 4387 | { |
no test coverage detected