Send a single raw SPI command frame at 512KHz (one chip-select assertion).
| 368 | |
| 369 | // Send a single raw SPI command frame at 512KHz (one chip-select assertion). |
| 370 | static Result SPISendCommand8MB(const u8* cmd, u32 cmdSize) |
| 371 | { |
| 372 | u8 transferOp = pxiDevMakeTransferOption(BAUDRATE_512KHZ, BUSMODE_1BIT); |
| 373 | u64 waitOp = pxiDevMakeWaitOperation(WAIT_NONE, DEASSERT_NONE, 0LL); |
| 374 | u64 dummy = 0; |
| 375 | |
| 376 | PXIDEV_SPIBuffer headerBuffer = {&dummy, 0U, transferOp, waitOp}; |
| 377 | PXIDEV_SPIBuffer cmdBuffer = {(void*)cmd, cmdSize, transferOp, waitOp}; |
| 378 | PXIDEV_SPIBuffer nullBuffer = {NULL, 0U, transferOp, waitOp}; |
| 379 | PXIDEV_SPIBuffer footerBuffer = {&dummy, 0U, transferOp, waitOp}; |
| 380 | |
| 381 | return PXIDEV_SPIMultiWriteRead(&headerBuffer, &cmdBuffer, &nullBuffer, &nullBuffer, &nullBuffer, &footerBuffer); |
| 382 | } |
| 383 | |
| 384 | // The 8MB flash cart ships write-protected: its status register has block-protect |
| 385 | // and SRWD bits set (observed sr = 0x84, then 0x86 once the write-enable latch is armed). READS work |