| 82 | } |
| 83 | |
| 84 | Result SPIEnableWriting(CardType type) |
| 85 | { |
| 86 | u8 cmd = SPI_CMD_WREN, statusReg = 0; |
| 87 | Result res = SPIWriteRead(type, &cmd, 1, NULL, 0, 0, 0); |
| 88 | int panic = 0; |
| 89 | |
| 90 | if (res || type == EEPROM_512B) |
| 91 | return res; // Weird, but works (otherwise we're getting an infinite loop for that chip type). |
| 92 | cmd = SPI_CMD_RDSR; |
| 93 | |
| 94 | // Bail out after a bounded number of polls instead of spinning forever. |
| 95 | // The actual precondition for a write is that the write-enable latch (WEL) is set. The 8MB |
| 96 | // cart legitimately leaves block-protect/SRWD bits set in the status register even when armed for |
| 97 | // writing (sr stays 0x86, and those bits cannot be cleared via WRSR — SRWD + WP# hardware-lock |
| 98 | // them), so for it we only require WEL. Every other chip clears to a bare 0x02 after WREN, so the |
| 99 | // stricter "nothing but WEL set" check is kept for them to preserve existing behaviour. |
| 100 | do { |
| 101 | res = SPIWriteRead(type, &cmd, 1, &statusReg, 1, 0, 0); |
| 102 | if (res) |
| 103 | return res; |
| 104 | if (type == FLASH_8MB) { |
| 105 | if (statusReg & SPI_FLG_WEL) |
| 106 | break; |
| 107 | } |
| 108 | else if (!(statusReg & ~SPI_FLG_WEL)) { |
| 109 | break; |
| 110 | } |
| 111 | } while (++panic < 1000); |
| 112 | |
| 113 | return panic >= 1000 ? 1 : 0; |
| 114 | } |
| 115 | |
| 116 | Result SPIReadJEDECIDAndStatusReg(CardType type, u32* id, u8* statusReg) |
| 117 | { |
no test coverage detected