(self)
| 37 | self.log(f"unexpected state in start(read={read}): state:{self.state} reg:{self.reg} data:{self.data}") |
| 38 | |
| 39 | def stop(self): |
| 40 | if self.state == CD3217Tracer.State.REQUEST and len(self.data) == 0: |
| 41 | return |
| 42 | |
| 43 | msg = f"Txn: {self.addr:02x}." |
| 44 | if self.state == CD3217Tracer.State.REQUEST: |
| 45 | msg += f"r [{self.reg:02x}]" |
| 46 | elif self.state == CD3217Tracer.State.WRITE: |
| 47 | msg += f"w [{self.reg:02x}]" |
| 48 | elif self.state == CD3217Tracer.State.READ: |
| 49 | msg += f"r [xx]" |
| 50 | else: |
| 51 | self.log(f"unexpected state in stop(): state:{self.state} reg:{self.reg} data:{self.data}") |
| 52 | self.reset() |
| 53 | return |
| 54 | |
| 55 | # only for debugging as some mismatches are expected as |
| 56 | # cd3217 seems to report the register size and not the number |
| 57 | # of requested bytes (or I2CDevTracer truncates reads). |
| 58 | #if self.length is not None and self.length > len(self.data): |
| 59 | # self.log(f"length {self.length:02x} mismatch received data: {len(self.data):02x}") |
| 60 | |
| 61 | for data in self.data: |
| 62 | msg += f" {data:02x}" |
| 63 | |
| 64 | self.log(msg) |
| 65 | self.reset() |
| 66 | |
| 67 | def read(self, data): |
| 68 | self.data.append(data) |
no test coverage detected