| 7 | from .sysreg import * |
| 8 | |
| 9 | class GPIOLogicAnalyzer(Reloadable): |
| 10 | def __init__(self, u, node=None, pins={}, regs={}, div=1, cpu=1, on_pin_change=True, on_reg_change=True): |
| 11 | self.u = u |
| 12 | self.p = u.proxy |
| 13 | self.iface = u.iface |
| 14 | self.cpu = cpu |
| 15 | self.base = 0 |
| 16 | if node is not None: |
| 17 | self.base = u.adt[node].get_reg(0)[0] |
| 18 | else: |
| 19 | on_pin_change=False |
| 20 | self.node = node |
| 21 | self.pins = pins |
| 22 | self.regs = regs |
| 23 | assert len(pins) <= 32 |
| 24 | assert div > 0 |
| 25 | self.div = div |
| 26 | self.cbuf = self.u.malloc(0x1000) |
| 27 | self.dbuf = None |
| 28 | self.on_pin_change = on_pin_change |
| 29 | self.on_reg_change = on_reg_change |
| 30 | self.p.mmu_init_secondary(cpu) |
| 31 | self.tfreq = u.mrs(CNTFRQ_EL0) |
| 32 | |
| 33 | def load_regmap(self, regmap, skip=set(), regs=set()): |
| 34 | base = regmap._base |
| 35 | for name, (addr, rcls) in regmap._namemap.items(): |
| 36 | if name not in skip and (not regs or name in regs): |
| 37 | self.regs[name] = base + addr, rcls |
| 38 | |
| 39 | def start(self, ticks, bufsize=0x10000): |
| 40 | self.bufsize = bufsize |
| 41 | if self.dbuf: |
| 42 | self.u.free(self.dbuf) |
| 43 | self.dbuf = self.u.malloc(bufsize) |
| 44 | |
| 45 | text = f""" |
| 46 | trace: |
| 47 | mov x16, x2 |
| 48 | add x3, x3, x2 |
| 49 | add x2, x2, #4 |
| 50 | mov x12, #-8 |
| 51 | mov x10, x2 |
| 52 | mov x6, #-1 |
| 53 | mov x7, #0 |
| 54 | ldr x8, ={self.base} |
| 55 | mrs x4, CNTPCT_EL0 |
| 56 | isb |
| 57 | 1: |
| 58 | ldr w15, [x16] |
| 59 | cmp w15, #1 |
| 60 | b.eq done |
| 61 | add x4, x4, x1 |
| 62 | 2: |
| 63 | mrs x5, CNTPCT_EL0 |
| 64 | isb |
| 65 | """ |
| 66 | if self.div > 1: |
no outgoing calls
no test coverage detected