| 123 | } |
| 124 | |
| 125 | static inline void handleCANInterrupt(uint8_t phys_index, uint8_t line_index) |
| 126 | { |
| 127 | const int8_t iface_index = can_iface_to_idx[phys_index]; |
| 128 | if (iface_index < 0 || iface_index >= HAL_NUM_CAN_IFACES) { |
| 129 | return; |
| 130 | } |
| 131 | if (!driver_initialised(iface_index)) { |
| 132 | //Just reset all the interrupts and return |
| 133 | CANIface::Can[iface_index]->IR = FDCAN_IR_RF0N; |
| 134 | CANIface::Can[iface_index]->IR = FDCAN_IR_RF1N; |
| 135 | CANIface::Can[iface_index]->IR = FDCAN_IR_TEFN; |
| 136 | return; |
| 137 | } |
| 138 | if (line_index == 0) { |
| 139 | if ((CANIface::Can[iface_index]->IR & FDCAN_IR_RF0N) || |
| 140 | (CANIface::Can[iface_index]->IR & FDCAN_IR_RF0F)) { |
| 141 | CANIface::Can[iface_index]->IR = FDCAN_IR_RF0N | FDCAN_IR_RF0F; |
| 142 | can_ifaces[iface_index]->handleRxInterrupt(0); |
| 143 | } |
| 144 | if ((CANIface::Can[iface_index]->IR & FDCAN_IR_RF1N) || |
| 145 | (CANIface::Can[iface_index]->IR & FDCAN_IR_RF1F)) { |
| 146 | CANIface::Can[iface_index]->IR = FDCAN_IR_RF1N | FDCAN_IR_RF1F; |
| 147 | can_ifaces[iface_index]->handleRxInterrupt(1); |
| 148 | } |
| 149 | } else { |
| 150 | if (CANIface::Can[iface_index]->IR & FDCAN_IR_TC) { |
| 151 | CANIface::Can[iface_index]->IR = FDCAN_IR_TC; |
| 152 | uint64_t timestamp_us = AP_HAL::micros64(); |
| 153 | if (timestamp_us > 0) { |
| 154 | timestamp_us--; |
| 155 | } |
| 156 | can_ifaces[iface_index]->handleTxCompleteInterrupt(timestamp_us); |
| 157 | } |
| 158 | |
| 159 | if ((CANIface::Can[iface_index]->IR & FDCAN_IR_BO)) { |
| 160 | CANIface::Can[iface_index]->IR = FDCAN_IR_BO; |
| 161 | can_ifaces[iface_index]->handleBusOffInterrupt(); |
| 162 | } |
| 163 | } |
| 164 | can_ifaces[iface_index]->pollErrorFlagsFromISR(); |
| 165 | } |
| 166 | |
| 167 | uint32_t CANIface::FDCANMessageRAMOffset_ = 0; |
| 168 |
no test coverage detected