| 145 | //----------------------------------------------------------------------------- |
| 146 | |
| 147 | void SY6522::Write(BYTE nReg, BYTE nValue) |
| 148 | { |
| 149 | switch (nReg) |
| 150 | { |
| 151 | case 0x00: // ORB |
| 152 | m_regs.ORB = nValue & m_regs.DDRB; |
| 153 | break; |
| 154 | case 0x01: // ORA |
| 155 | case 0x0f: // ORA_NO_HS |
| 156 | m_regs.ORA = nValue & m_regs.DDRA; |
| 157 | break; |
| 158 | case 0x02: // DDRB |
| 159 | m_regs.DDRB = nValue; |
| 160 | break; |
| 161 | case 0x03: // DDRA |
| 162 | m_regs.DDRA = nValue; |
| 163 | break; |
| 164 | case 0x04: // TIMER1L_COUNTER |
| 165 | case 0x06: // TIMER1L_LATCH |
| 166 | m_regs.TIMER1_LATCH.l = nValue; |
| 167 | break; |
| 168 | case 0x05: // TIMER1H_COUNTER |
| 169 | { |
| 170 | UpdateIFR(IxR_TIMER1); // Clear Timer1 Interrupt Flag |
| 171 | m_regs.TIMER1_LATCH.h = nValue; |
| 172 | m_regs.TIMER1_COUNTER.w = SetTimerSyncEvent(nReg, m_regs.TIMER1_LATCH.w); |
| 173 | StartTimer1(); |
| 174 | } |
| 175 | break; |
| 176 | case 0x07: // TIMER1H_LATCH |
| 177 | UpdateIFR(IxR_TIMER1); // Clear Timer1 Interrupt Flag |
| 178 | m_regs.TIMER1_LATCH.h = nValue; |
| 179 | break; |
| 180 | case 0x08: // TIMER2L |
| 181 | m_regs.TIMER2_LATCH.l = nValue; |
| 182 | break; |
| 183 | case 0x09: // TIMER2H |
| 184 | { |
| 185 | UpdateIFR(IxR_TIMER2); // Clear Timer2 Interrupt Flag |
| 186 | m_regs.TIMER2_LATCH.h = nValue; // NB. Real 6522 doesn't have TIMER2_LATCH.h |
| 187 | m_regs.TIMER2_COUNTER.w = SetTimerSyncEvent(nReg, m_regs.TIMER2_LATCH.w); |
| 188 | StartTimer2(); |
| 189 | } |
| 190 | break; |
| 191 | case 0x0a: // SERIAL_SHIFT |
| 192 | break; |
| 193 | case 0x0b: // ACR |
| 194 | m_regs.ACR = nValue; |
| 195 | break; |
| 196 | case 0x0c: // PCR - Used for Speech chip only |
| 197 | m_regs.PCR = nValue; |
| 198 | break; |
| 199 | case 0x0d: // IFR |
| 200 | // - Clear those bits which are set in the lower 7 bits. |
| 201 | // - Can't clear bit 7 directly. |
| 202 | UpdateIFR(nValue); |
| 203 | break; |
| 204 | case 0x0e: // IER |
no outgoing calls
no test coverage detected