===========================================================================
| 1175 | |
| 1176 | //=========================================================================== |
| 1177 | bool _CheckBreakpointValueWithPrefix(Breakpoint_t* pBP, int nVal) |
| 1178 | { |
| 1179 | bool bStatus = false; |
| 1180 | int iCmp = pBP->eOperator; |
| 1181 | |
| 1182 | bool isRead = pBP->eSource == BP_SRC_MEM_RW || pBP->eSource == BP_SRC_MEM_READ_ONLY || pBP->eSource == BP_SRC_REG_PC; |
| 1183 | bool isWrite = pBP->eSource == BP_SRC_MEM_RW || pBP->eSource == BP_SRC_MEM_WRITE_ONLY; |
| 1184 | |
| 1185 | // If no prefix filters, then BP hit |
| 1186 | if (pBP->addrPrefix.nSlot == AddressPrefix_t::kSlotInvalid |
| 1187 | && pBP->addrPrefix.nBank == AddressPrefix_t::kBankInvalid |
| 1188 | && pBP->addrPrefix.nLangCard == AddressPrefix_t::kLangCardInvalid |
| 1189 | && pBP->addrPrefix.bIsROM == false) |
| 1190 | return true; |
| 1191 | |
| 1192 | // Prefix filters only apply for BP_OP_EQUAL operation (for now) |
| 1193 | if (iCmp != BP_OP_EQUAL) |
| 1194 | return true; |
| 1195 | |
| 1196 | // Apply any prefix filters |
| 1197 | |
| 1198 | const UINT ramworksActiveBank = GetRamWorksActiveBank() + 1; // [0x01..0x100] |
| 1199 | |
| 1200 | if (nVal <= _6502_STACK_END) |
| 1201 | { |
| 1202 | if ((pBP->addrPrefix.nBank == 0x00 && !(GetMemMode() & MF_ALTZP)) |
| 1203 | || (pBP->addrPrefix.nBank == ramworksActiveBank && (GetMemMode() & MF_ALTZP))) |
| 1204 | { |
| 1205 | bStatus = true; |
| 1206 | } |
| 1207 | } |
| 1208 | else if (TEXT_PAGE1_BEGIN <= nVal && nVal <= 0x7FF && (GetMemMode() & MF_80STORE)) |
| 1209 | { |
| 1210 | if ((pBP->addrPrefix.nBank == 0x00 && !(GetMemMode() & MF_PAGE2)) |
| 1211 | || (pBP->addrPrefix.nBank == ramworksActiveBank && (GetMemMode() & MF_PAGE2))) |
| 1212 | { |
| 1213 | bStatus = true; |
| 1214 | } |
| 1215 | } |
| 1216 | else if (HGR_PAGE1_BEGIN <= nVal && nVal <= 0x3FFF && ((GetMemMode() & (MF_80STORE | MF_HIRES)) == (MF_80STORE | MF_HIRES))) |
| 1217 | { |
| 1218 | if ((pBP->addrPrefix.nBank == 0x00 && !(GetMemMode() & MF_PAGE2)) |
| 1219 | || (pBP->addrPrefix.nBank == ramworksActiveBank && (GetMemMode() & MF_PAGE2))) |
| 1220 | { |
| 1221 | bStatus = true; |
| 1222 | } |
| 1223 | } |
| 1224 | else if (nVal <= 0xBFFF) |
| 1225 | { |
| 1226 | if (isRead) |
| 1227 | { |
| 1228 | if ((pBP->addrPrefix.nBank == 0x00 && !(GetMemMode() & MF_AUXREAD)) |
| 1229 | || (pBP->addrPrefix.nBank == ramworksActiveBank && (GetMemMode() & MF_AUXREAD))) |
| 1230 | { |
| 1231 | bStatus = true; |
| 1232 | } |
| 1233 | } |
| 1234 | if (isWrite) |
no test coverage detected