Method validate

src/gpu/cl/kernels/ClScatterKernel.cpp:56–112

}

Status ClScatterKernel::validate(const ITensorInfo *updates,
                                 const ITensorInfo *indices,
                                 const ITensorInfo *dst,
                                 const ScatterInfo &info)
{
    ARM_COMPUTE_UNUSED(info);
    ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(updates, indices, dst);
    ARM_COMPUTE_RETURN_ERROR_ON_SIZE_UNSUPPORTED(updates, indices, dst);

    const TensorShape &ind_shape = indices->tensor_shape();
    const TensorShape &upt_shape = updates->tensor_shape();
    const TensorShape &dst_shape = dst->tensor_shape();

    const int32_t upt_dims = upt_shape.num_dimensions();
    const int32_t dst_dims = dst_shape.num_dimensions();
    const int32_t ind_dims = ind_shape.num_dimensions();
    const int32_t data_dim = upt_dims - (ind_dims - 1); // Number of batch dims is the number of indices dims - 1

    const int32_t index_len = ind_shape[0];
    bool          unsupported_padding_config =
        (dst_dims == index_len) && index_len > 1 && (dst->has_padding() || updates->has_padding());

    ARM_COMPUTE_RETURN_ERROR_ON_MSG(unsupported_padding_config, "Padding is not supported with these shapes.");
    ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(updates, dst);
    ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_NOT_IN(indices, DataType::S32);
    ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_NOT_IN(dst, DataType::F32, DataType::F16, DataType::S32, DataType::S16,
                                                 DataType::S8, DataType::U32, DataType::U16, DataType::U8);

    // Check data dims in update tensor and output tensor are equal
    for (int32_t i = 0; i < data_dim; i++)
    {
        ARM_COMPUTE_RETURN_ERROR_ON_MSG(upt_shape[i] != dst_shape[i],
                                        "Data dims should be same size in both updates and ouput tensor.");
    }

    // Check if batch dims in indices and updates tensor are equal.
    for (int32_t i = 0; i < ind_dims - 1; i++)
    {
        ARM_COMPUTE_RETURN_ERROR_ON_MSG(upt_shape[data_dim + i] != ind_shape[i + 1],
                                        "Batch dimensions should be the same in updates and indices tensor.");
    }

    ARM_COMPUTE_RETURN_ERROR_ON_MSG(ind_shape[1] != upt_shape[data_dim],
                                    "Height of indices tensor should match size of highest dimension in updates tensor "
                                    "(Excluding batch dimension)");

    ARM_COMPUTE_RETURN_ERROR_ON_MSG(
        data_dim >= dst_dims, "Update tensor cannot have more dims than output tensor. (Excluding batch dimensions)");
    ARM_COMPUTE_RETURN_ERROR_ON(index_len != dst_dims - data_dim);
    ARM_COMPUTE_RETURN_ERROR_ON_MSG((ind_dims < 2), "Shape of Indices tensor must be at least 2D");

    ARM_COMPUTE_RETURN_ERROR_ON_MSG(index_len > max_index_length, "Maximum supported index length is 5!");
    ARM_COMPUTE_RETURN_ERROR_ON_MSG(index_len > dst_dims && dst_dims != 1,
                                    "Index length should be smaller than or equal to number of output dims");

    return Status{};
}