| 501 | } |
| 502 | |
| 503 | void CpuFullyConnected::run(ITensorPack &tensors) |
| 504 | { |
| 505 | ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "CpuFullyConnected::run"); |
| 506 | prepare(tensors); |
| 507 | |
| 508 | #ifdef ARM_COMPUTE_ASSERTS_ENABLED |
| 509 | ++_asrt_run_count; |
| 510 | ARM_COMPUTE_ERROR_ON(_dynamic_weights && _asrt_prepare_count != _asrt_run_count); |
| 511 | #endif // ARM_COMPUTE_ASSERTS_ENABLED |
| 512 | |
| 513 | auto src = tensors.get_const_tensor(ACL_SRC_0); |
| 514 | |
| 515 | CpuAuxTensorHandler flattened_src(offset_int_vec(FlattenedSrc), _flattened_src, tensors, false); |
| 516 | CpuAuxTensorHandler transformed_wei(offset_int_vec(_trans_weights_idx), _trans_weights, tensors, false); |
| 517 | |
| 518 | // Linearize src if it comes from a convolutional layer |
| 519 | if (_is_fc_after_conv) |
| 520 | { |
| 521 | ITensorPack flatten_pack{{ACL_SRC, src}, {ACL_DST, flattened_src.get()}}; |
| 522 | _flatten->run(flatten_pack); |
| 523 | } |
| 524 | |
| 525 | ITensorPack gemm_pack = tensors; |
| 526 | gemm_pack.add_const_tensor(ACL_SRC_0, (_is_fc_after_conv) ? flattened_src.get() : src); |
| 527 | if (_needs_weights_reshape || _needs_weights_conversion) |
| 528 | { |
| 529 | gemm_pack.add_const_tensor(ACL_SRC_1, transformed_wei.get()); |
| 530 | } |
| 531 | |
| 532 | // Run matrix multiply |
| 533 | if (_is_quantized_asymmetric) |
| 534 | { |
| 535 | _mm_gemmlowp->run(gemm_pack); |
| 536 | } |
| 537 | else |
| 538 | { |
| 539 | _mm_gemm->run(gemm_pack); |
| 540 | } |
| 541 | } |
| 542 | |
| 543 | void CpuFullyConnected::prepare(ITensorPack &tensors) |
| 544 | { |
no test coverage detected