Function validate_arguments

src/cpu/kernels/CpuTopKVKernel.cpp:86–139

     REGISTER_QASYMM8_SIGNED_NEON(arm_compute::cpu::topkv_qasymm8_signed_neon)}};

Status
validate_arguments(const ITensorInfo &predictions, const ITensorInfo &targets, const ITensorInfo &dst, uint32_t k)
{
    ARM_COMPUTE_RETURN_ERROR_ON_SIZE_UNSUPPORTED(&predictions, &targets);
    ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(&predictions);

    // predictions (logical shape [C, N], where N defaults to 1 if dimension 1 is absent)
    ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(&predictions, ITensorInfo::one_channel, DataType::QASYMM8,
                                                         DataType::QASYMM8_SIGNED, DataType::S32, DataType::F16,
                                                         DataType::F32);

    // targets (class indices)
    ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(&targets, ITensorInfo::one_channel, DataType::U32);

    const unsigned int C = predictions.tensor_shape()[0]; // classes
    const unsigned int N = predictions.tensor_shape()[1]; // batch (defaults to 1 if not present)

    // k constraints
    ARM_COMPUTE_RETURN_ERROR_ON_MSG(k == 0, "k must be > 0");
    ARM_COMPUTE_RETURN_ERROR_ON_MSG(C == 0, "predictions classes dimension must be > 0");
    ARM_COMPUTE_RETURN_ERROR_ON_MSG(N == 0, "predictions batch dimension must be > 0");
    ARM_COMPUTE_RETURN_ERROR_ON_MSG(k > C, "k must be <= number of classes (C)");

    // targets must match batch
    // targets is expected to contain N elements (shape [N])
    ARM_COMPUTE_RETURN_ERROR_ON_MSG(targets.tensor_shape()[0] != N,
                                    "targets dimension must match predictions batch dimension (N)");

    ARM_COMPUTE_RETURN_ERROR_ON(predictions.num_dimensions() > 2);
    ARM_COMPUTE_RETURN_ERROR_ON(targets.num_dimensions() > 1);

    // Output is one byte per batch element: shape [N]
    const TensorShape out_shape(N);

    // If dst is already configured, validate it
    if (dst.total_size() != 0)
    {
        ARM_COMPUTE_RETURN_ERROR_ON_SIZE_UNSUPPORTED(&dst);
        ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(&dst, ITensorInfo::one_channel, DataType::U8);
        ARM_COMPUTE_RETURN_ERROR_ON_MSG(dst.tensor_shape() != out_shape, "dst shape must be [N]");
    }
    else
    {
        const auto dst_info = TensorInfo(out_shape, ITensorInfo::one_channel, DataType::U8);
        ARM_COMPUTE_RETURN_ERROR_ON_SIZE_UNSUPPORTED(&dst_info);
    }

    const auto uk = CpuTopKVKernel::get_implementation<CpuTopKVKernelDataTypeISASelectorData>(
        CpuTopKVKernelDataTypeISASelectorData{predictions.data_type(), CPUInfo::get().get_isa()});

    ARM_COMPUTE_RETURN_ERROR_ON(uk == nullptr || uk->ukernel == nullptr);

    return Status{};
}

} // namespace