| 63 | REGISTER_QASYMM8_SIGNED_NEON(directconv3d_qs8_neon_ndhwc)}}; |
| 64 | |
| 65 | Status validate_arguments(const ITensorInfo *src0, |
| 66 | const ITensorInfo *src1, |
| 67 | const ITensorInfo *src2, |
| 68 | const ITensorInfo *dst, |
| 69 | const Conv3dInfo &conv_info) |
| 70 | { |
| 71 | ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src0, src1, dst); |
| 72 | ARM_COMPUTE_RETURN_ERROR_ON_SIZE_UNSUPPORTED(src0, src1); |
| 73 | ARM_COMPUTE_RETURN_ERROR_ON(src0->data_layout() != DataLayout::NDHWC); |
| 74 | ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_LAYOUT(src0, src1, dst); |
| 75 | ARM_COMPUTE_RETURN_ERROR_ON_CPU_F16_UNSUPPORTED(src0); |
| 76 | ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(src0, 1, DataType::F16, DataType::F32, DataType::QASYMM8, |
| 77 | DataType::QASYMM8_SIGNED); |
| 78 | ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src0, src1); |
| 79 | ARM_COMPUTE_RETURN_ERROR_ON(conv_info.dilation != Size3D(1U, 1U, 1U)); |
| 80 | |
| 81 | const auto *uk = |
| 82 | CpuDirectConv3dKernel::get_implementation(DataTypeISASelectorData{src0->data_type(), CPUInfo::get().get_isa()}); |
| 83 | |
| 84 | ARM_COMPUTE_RETURN_ERROR_ON(uk == nullptr || uk->ukernel == nullptr); |
| 85 | |
| 86 | const DataLayout data_layout = src0->data_layout(); |
| 87 | const int channel_idx = get_data_layout_dimension_index(data_layout, DataLayoutDimension::CHANNEL); |
| 88 | |
| 89 | // Weight layout is D, H, W, Cin, Cout |
| 90 | ARM_COMPUTE_RETURN_ERROR_ON(src1->num_dimensions() > 5); |
| 91 | ARM_COMPUTE_RETURN_ERROR_ON(src1->dimension(1) != src0->dimension(channel_idx)); |
| 92 | |
| 93 | if (src2 != nullptr) |
| 94 | { |
| 95 | ARM_COMPUTE_RETURN_ERROR_ON_SIZE_UNSUPPORTED(src2); |
| 96 | if (is_data_type_quantized(src0->data_type())) |
| 97 | { |
| 98 | ARM_COMPUTE_RETURN_ERROR_ON_DATA_TYPE_CHANNEL_NOT_IN(src2, 1, DataType::S32); |
| 99 | } |
| 100 | else |
| 101 | { |
| 102 | ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DATA_TYPES(src1, src2); |
| 103 | } |
| 104 | ARM_COMPUTE_RETURN_ERROR_ON_MSG(src2->dimension(0) != src1->dimension(0), |
| 105 | "Biases size and number of dst feature maps should match"); |
| 106 | ARM_COMPUTE_RETURN_ERROR_ON_MSG(src2->num_dimensions() > 1, "Biases should be one dimensional"); |
| 107 | } |
| 108 | |
| 109 | const TensorShape output_shape = |
| 110 | misc::shape_calculator::compute_conv3d_shape(src0->tensor_shape(), src1->tensor_shape(), conv_info); |
| 111 | |
| 112 | // Checks performed when output is configured |
| 113 | if (dst->total_size() != 0) |
| 114 | { |
| 115 | ARM_COMPUTE_RETURN_ERROR_ON_SIZE_UNSUPPORTED(dst); |
| 116 | ARM_COMPUTE_RETURN_ERROR_ON_MISMATCHING_DIMENSIONS(dst->tensor_shape(), output_shape); |
| 117 | ARM_COMPUTE_RETURN_ERROR_ON(dst->data_type() != src0->data_type()); |
| 118 | } |
| 119 | else |
| 120 | { |
| 121 | const TensorInfo dst_info(output_shape, src0->num_channels(), src0->data_type()); |
| 122 | ARM_COMPUTE_RETURN_ERROR_ON_SIZE_UNSUPPORTED(&dst_info); |
no test coverage detected